Troubleshooting and implementation of EdDSA algorithm in Vivado Design Suite

I am looking for an FPGA (Verilog) expert who can help me to troubleshoot and implement the EdDSA algorithm in Xilinx Vivado Design Suite. The Vivado project file is available in the attachments and several modules of the project are already completed. Looking for an expert who can do it in 3 to 4 days. Further information will be provided in the discussion.