Simple FSM using verilog
Budget: $10 – $30 USD
Implement a FSM to detect a sequence of “101”.
(Ex: 10101: will be detected as two “101”; 101101: will be detected as two “101”)
• The input sequence is set by using the 16 switches.
• Reset and read sequence are enabled by the push buttons.
• Output, status, and current sequence position are displayed on the 7-Segment[3:0].
(Ex: 10101: will be detected as two “101”; 101101: will be detected as two “101”)
• The input sequence is set by using the 16 switches.
• Reset and read sequence are enabled by the push buttons.
• Output, status, and current sequence position are displayed on the 7-Segment[3:0].
Related categories:
Verilog / VHDL