Review VHDL Code
Budget: $250 – $750 USD
We've written some VHDL code for FPGA we need someone to adapt it to our coding standard.
we will share a report of all violations for a set of files and the VHDL code shall be modified as specified in the coding standard.
To make an example all signals shall be names s_<signal_name>,
signal test_sig : std_logic; -- violation!
signal s_test_sig : std_logic; -- correct
the code will be shared with a Gitlab repo, a dedicatd branch will be created to modify the original code.
the code shall be compiled, to chekc no errors were introduced. as soon as the code is delivered we wil rerun the checker to chek for residual errors, and we would provide a feedback (unless the freelancer has the same checker tool)
we will share a report of all violations for a set of files and the VHDL code shall be modified as specified in the coding standard.
To make an example all signals shall be names s_<signal_name>,
signal test_sig : std_logic; -- violation!
signal s_test_sig : std_logic; -- correct
the code will be shared with a Gitlab repo, a dedicatd branch will be created to modify the original code.
the code shall be compiled, to chekc no errors were introduced. as soon as the code is delivered we wil rerun the checker to chek for residual errors, and we would provide a feedback (unless the freelancer has the same checker tool)