RTL Designer (verilog) needed.

Job ID: 30771397

Budget: ₹1,500 – ₹12,500 INR

I have a cryptographic algorithm written in Verilog in purely combinational logic. It has a large table and that table is exhausting most of the LUTs. So, I want the code to be implemented in sequential logic and use block RAM for holding the table to increase LUT utilization for RTL logic.

Related categories: Electronics Verilog / VHDL Electrical Engineering FPGA Electronic Design