Quick help needed on coming up with a dynamic Allocation of 2-Dimension System Verilog port
Budget: $10 – $30 USD
I have a localparamter declared in my SystemVerilog like this (y is another Parameter) :
localparam x = y ? 4 : 1 ,
Then I have a RTL port which is something like this (where z is another parameter):
input logic [x-1:0][((z+1)*8-1):0] port1,
But I want to use 'y' directly in this port1 instead of x.
Can I somehow use 'y' instead of x to dynamically allocate the value of it. It should be able to compile/elaborate.
Should be quick
localparam x = y ? 4 : 1 ,
Then I have a RTL port which is something like this (where z is another parameter):
input logic [x-1:0][((z+1)*8-1):0] port1,
But I want to use 'y' directly in this port1 instead of x.
Can I somehow use 'y' instead of x to dynamically allocate the value of it. It should be able to compile/elaborate.
Should be quick