Quartus, FPGA technology, VHDL, ModelSim, 3-ported RAM, LPM, MIF file, MIPS R-type instruction

Job ID: 31806725

Budget: $10 – $30 USD

modelsim is must
Add-Sub unit with Register file (3-ported RAM)
3-ported register file, 32 bit registers, add/sub unit.

Related categories: Electronics Verilog / VHDL Electrical Engineering Circuit Design FPGA