Pipelining the Small16 Processor
Budget: $8 – $15 USD
In this lab exercise, you will pipeline the Small16 microprocessor from your solution to lab 3. A diagram of the new pipelined datapath is provided below. This pipelined processor will only execute instructions sequentially (it will not support jump instructions); therefore, the processor will not have to worry about control hazards. Please remove your support for jump instructions in your control and datapath. Also assume that the instructions you execute will not have any data hazards. For this lab, you will not have to worry about any data forwarding or hazard mitigation techniques.
You will need to modify your lab 3 VHDL code, including your datapath, control, and processor; for the control, I recommend making separate control combinational logic for each stage of the pipeline. You may also want to modify test_processor.vhd and increase the duration of the simulation; you can do this by increasing how many clock cycles are simulated within the stimulus process. Refer to Canvas for additional VHDL source files which will be needed in your pipelined design. Remove VHDL source files (from lab 3) which are not necessary for your pipelined design. Use the instruction code found in the new instruction memory VHDL source file to test this system.
You will need to modify your lab 3 VHDL code, including your datapath, control, and processor; for the control, I recommend making separate control combinational logic for each stage of the pipeline. You may also want to modify test_processor.vhd and increase the duration of the simulation; you can do this by increasing how many clock cycles are simulated within the stimulus process. Refer to Canvas for additional VHDL source files which will be needed in your pipelined design. Remove VHDL source files (from lab 3) which are not necessary for your pipelined design. Use the instruction code found in the new instruction memory VHDL source file to test this system.