Permutation enumeration counter - Xilinx Zynq7010 EBAZ Verilog FPGA design

I am looking for a skilled FPGA designer with experience in Xilinx Zynq7010 EBAZ Verilog to develop a permutation enumeration counter. The counter should have the following functionality and requirements:

Functionality:
- The counter should be able to increment indefinitely.
- The counter shall initialize to the starting position on reset.
- The counter shall toggle a minimum number of bits, like Grey Code.

Requirements:
- The project should be implemented using Verilog for Xilinx Zynq7010 EBAZ board.

The Verilog function shall be parameterized PermCtr(K, N)
- The counter should be designed to efficiently handle permutation enumeration.
- The design should be optimized for performance and resource utilization.

Additional Information:
- There is no specific maximum count or value that the counter should reach.
- No additional features such as pause/resume option are required.

Ideal Skills and Experience:
- Strong knowledge and experience in FPGA design using Xilinx Zynq7010 EBAZ Verilog.
- Understanding of Permutation enumeration and efficient counter design.
- Proficiency in optimizing design for performance and resource utilization.

If you have the necessary skills and experience, please submit your proposal for this project.