Modify the Code of Simple SPI Master in Verilog
Budget: ₹600 – ₹1,000 INR
I have written the code for a simle SPI Master in verilog and also included a testbench. I want you to:
1) Add a Clock Divider to it, so that the output SPI frequecy is 1MHz
2) There are 3 SPI commands: (1) one write command, (2) multiple write command, (3) one read command. Modify the SPI master Verilog code to implement these 3 commands. Ideally, I want to specify (i) write or read, (ii) number of bytes if write command, (iii) address, (iv) data, then the code will automatically generate the correct checksum and dummy bytes.
Would appreciate if the work could be finished as soon as possible. Thanks!
1) Add a Clock Divider to it, so that the output SPI frequecy is 1MHz
2) There are 3 SPI commands: (1) one write command, (2) multiple write command, (3) one read command. Modify the SPI master Verilog code to implement these 3 commands. Ideally, I want to specify (i) write or read, (ii) number of bytes if write command, (iii) address, (iv) data, then the code will automatically generate the correct checksum and dummy bytes.
Would appreciate if the work could be finished as soon as possible. Thanks!