Looking an Experienced FPGA Developer for UFS Host device
Budget: $5,000 – $10,000 USD
using Artix 7 implement Master UFS protocol design for the UFS Host device,
Feel free to contact who's have experince on Stroage's(emmc, ufs, nand e.t.c)
Skills required : Verilog , VHDL , C , C++
Feel free to contact who's have experince on Stroage's(emmc, ufs, nand e.t.c)
Skills required : Verilog , VHDL , C , C++