Implementation of FIR filters using various algorithms

FIR filter has a number of useful properties compared to an IIR filter i.e. inherently stable, no feedback require, designed to be linear phase.Finite Impulse response (FIR) with low cost and high performance and its its implementation using various algorithm may be extended for observation of an elaborate analysis about hardware implementations of FIR filters using different algorithm i.e., Distributed Arithmetic (DA), DA-Offset binary coding(DA-OBC), Common SubExpression Elimination(CSE) and Sum-of-power-of-two(SOPOT) with less resources and without affecting the performance of the origical FIR filter. So According to our survey, DA structure is easy to implement on FPGA because of pre calculated results are already stored in LUTs and in FPGA it is easy to design. The CSE algorithm is used to find and eliminate most common event among filter coefficient which results in power and area saving by reducing multiplier with a small number of adders while implemented in FIR filters.