HLS Algorithm Implementation
Budget: $30 – $250 USD
I'm seeking a talented freelancer with expertise in FPGA development to assist in implementing high-level synthesis (HLS) algorithms on the Vitis platform. I have a solid background in HLS but need guidance with Vitis integration.
Requirements:
• Experience with Vitis platform and HLS technology
• Proficiency in Verilog programming
• Past work with image, data encryption, or signal processing algorithms.
Ideal Skills:
• FPGA design and development
• HLS algorithm optimization for performance
• Familiarity with Xilinx development tools
• Ability to write clean, maintainable code
Goals:
• To effectively integrate HLS algorithms into a Vitis workflow
• To optimize algorithm performance on an FPGA architecture
I look forward to collaborating with a knowledgeable individual who can help bridge my HLS experience with the Vitis platform to achieve optimized algorithm performance.
Requirements:
• Experience with Vitis platform and HLS technology
• Proficiency in Verilog programming
• Past work with image, data encryption, or signal processing algorithms.
Ideal Skills:
• FPGA design and development
• HLS algorithm optimization for performance
• Familiarity with Xilinx development tools
• Ability to write clean, maintainable code
Goals:
• To effectively integrate HLS algorithms into a Vitis workflow
• To optimize algorithm performance on an FPGA architecture
I look forward to collaborating with a knowledgeable individual who can help bridge my HLS experience with the Vitis platform to achieve optimized algorithm performance.