Fpga project

1. "idle" state: It is the state when the machine is doing nothing and is idle. In "idle" state, if power button is "on" then the state transition takes place from state "idle" to state "a" and the output is low. If power button is "off ", then the state remains in "idle".
2. "a" state: In state "a", if fill_water is 1(that is if the water gets filled) then the state moves to state "b" otherwise it remains in state "a".
3. "b" state: It is the wash state of the machine. In "b" state, if add_det = 1(that is if the detergent is added) then the state moves to state "c" otherwise remain at state "b".
4. "c" state: It is the rinse state of the machine. In "c" state, if the water is filled that is if fill_water = 1, then the process gets completed and the state returns back to its idle state and the output is 1. Otherwise it remains in state "c".
and in state a it depends on weight for example :
0-2 kilo 3 seconds to fill water
3-5 kilos 5 seconds
6-7 kilos 8 seconds
for the weight 3bit for the switches



we want it in verilog code and the state diagram and FPGA DEMONSTRATION and testbench code