FPGA-in-the-Loop for a pv boost converter
Budget: $2 – $8 USD
I have a PV boost converter that I want to control using the MPC Laguerre method, and I’ve successfully implemented this. The system in Simulink works fine. Afterward, I replaced the MPC block, meaning the controller, with a discrete model, and it also worked well. I then used HDL Coder to convert the controller block into VHDL code, which was completed successfully.
In the final step, I used FIL Wizard to set up a communication interface between MATLAB and the FPGA board. My board is a Zybo Z7-20, which is not yet supported by MATLAB, so in the FIL Wizard, I manually added a customized board and selected JTAG USB communication. I provided the VHDL file generated by HDL Coder so that it could build the FPGA-in-the-Loop (FIL) block and send the bitstream to the FPGA. This step was successful, and I was able to deploy the code to the FPGA. I used a sampling time of 1 microsecond.
However, when I ran the simulation, I noticed that the results from the controller and the results generated by the FPGA were not the same. What I need now is to fix this issue and ensure that the results are identical or at least very close.
The requirements:
1- the Simulink simulation should be the same as the real time simulation FPGA in the loop the controled current have to be the same even if i change the reference it should follow this reference for both strategies
2- the system should work on my laptop and my zybo z7 20 board using the JTAG using remote access to manipulate on my laptop like anydesk
3- at the end you should tell me how you fixed the problem exactly ? by video or any method that you can use to explain your work
Thank you
In the final step, I used FIL Wizard to set up a communication interface between MATLAB and the FPGA board. My board is a Zybo Z7-20, which is not yet supported by MATLAB, so in the FIL Wizard, I manually added a customized board and selected JTAG USB communication. I provided the VHDL file generated by HDL Coder so that it could build the FPGA-in-the-Loop (FIL) block and send the bitstream to the FPGA. This step was successful, and I was able to deploy the code to the FPGA. I used a sampling time of 1 microsecond.
However, when I ran the simulation, I noticed that the results from the controller and the results generated by the FPGA were not the same. What I need now is to fix this issue and ensure that the results are identical or at least very close.
The requirements:
1- the Simulink simulation should be the same as the real time simulation FPGA in the loop the controled current have to be the same even if i change the reference it should follow this reference for both strategies
2- the system should work on my laptop and my zybo z7 20 board using the JTAG using remote access to manipulate on my laptop like anydesk
3- at the end you should tell me how you fixed the problem exactly ? by video or any method that you can use to explain your work
Thank you