FPGA Verilog Code Debugging

I'm seeking a professional with strong debugging skills and experience with Verilog code on FPGA using Vivado. The task involves identifying and rectifying issues with a specific piece of code.

Requirements:
- Debugging Verilog code for FPGA
- Experience with Vivado
- Understanding of communication transmission concepts

Project Details:
I have a complete set of code and files, but currently, the receive signal is not correct, resulting in incorrect data being received.

Ideal Freelancer:
- Proficient in Verilog and Vivado
- Strong debugging skills
- Experience with communication transmission concepts
- Chinese speaker preferred