FPGA Implementation of Viterbi Model for Image Processing
Budget: $250 – $750 USD
I'm looking for an experienced FPGA engineer, proficient with HLS, to implement the Viterbi (VIT) model on a Xilinx FPGA. The primary goal of this project is to significantly reduce the processing time for image data.
Key requirements:
- Extensive experience in FPGA programming, particularly with Xilinx platforms.
- Proficient in High-Level Synthesis (HLS).
- Prior experience with implementing the Viterbi model.
- Strong understanding of image data processing.
The ideal candidate will have a proven track record of successful FPGA projects, with the ability to deliver high-quality work under tight deadlines. Your expertise will help streamline our image data processing, making it faster and more efficient.
Key requirements:
- Extensive experience in FPGA programming, particularly with Xilinx platforms.
- Proficient in High-Level Synthesis (HLS).
- Prior experience with implementing the Viterbi model.
- Strong understanding of image data processing.
The ideal candidate will have a proven track record of successful FPGA projects, with the ability to deliver high-quality work under tight deadlines. Your expertise will help streamline our image data processing, making it faster and more efficient.