Digital Verilog

1) Frequency divider by - / 2n - / by any integer 2) Serial Peripheral Interface (SPI) - Both master and slave 3) UART TX/RX - Asynchronous serial communication - Start bit, Stop bit, over sampling etc. - Exercise on cross-clock domain synchronizer What to submit - RTL code (.v) with inline comment - Test bench (.v) with inline comment - Timing diagram (gtkwave) with annotation - Rough description of the corresponding circuit