Design 5 stage Pipelined MIPS CPU on Logisim

add, addi, sub, and, or, lw, sw, and beq (no additional instructions) should be implemented. Each instruction should be tested with some data
values. The pipeline should be stalled for data hazards or control hazards.

I'll need you to add a pdf file with brief circuit description, the truth tables, and tested instructions to ensure that the CPU is working correctly.