Design an ALU Using Verilog
Budget: $30 – $250 USD
Top cell : alu
I/O: bit 15 is the most significant bit. INPUTS: A(15:0) , B(15:0) , alu_code(4:0) ; OUTPUTS: C(15:0) overflow
TOP MODULE: 16-bit Adder Module
PRIMARY SIGNALS: BUS inputs/outputs and additional signals
BUS signals: bit 15 is the most significant bit. All bus signals are named with upper case letters INPUTS:
A[15:0], B[15:0],CODE[2:0] OUTPUTS: C[15:0]
The budget has limit of $80
More details in Chat!
I/O: bit 15 is the most significant bit. INPUTS: A(15:0) , B(15:0) , alu_code(4:0) ; OUTPUTS: C(15:0) overflow
TOP MODULE: 16-bit Adder Module
PRIMARY SIGNALS: BUS inputs/outputs and additional signals
BUS signals: bit 15 is the most significant bit. All bus signals are named with upper case letters INPUTS:
A[15:0], B[15:0],CODE[2:0] OUTPUTS: C[15:0]
The budget has limit of $80
More details in Chat!