DVB Packet Processor Development for iCE40 FPGA with Verilog

Verilog Development for ICE40UP5K FPGA - DVB Packet Processing

I am looking for a Verilog developer to create a DVB packet processor for the Lattice iCE40UP5K FPGA. The main task is to extract NIT packets from DVB transport streams and transmit them via serial port.

Project Requirements:
Develop Verilog code for Lattice iCE40UP5K FPGA
Input: 8-bit parallel data with clock (DVB transport stream)
Output: Serial transmission of extracted NIT packets
The code must work on my custom iCE40 development board

Additional Information:
A reference implementation in VHDL for Xilinx XC3S50AN is available and can be used as a guide The developer will have access to the existing VHDL code

Ongoing consultation and support will be required for:
Code development process
Implementation assistance
Testing and verification on the actual hardware


Required Skills:
Strong experience with Verilog HDL
Experience with Lattice iCE40 FPGAs
Understanding of DVB transport stream protocol
Good communication skills for technical discussions

Please include in your proposal:
Your experience with similar FPGA projects
Your familiarity with DVB protocols
Estimated timeline for completion
Your approach to providing implementation support