CA-CFAR implementation in VHDL with complex data processing
Budget: ₹1,500 – ₹12,500 INR
We have developed a CA-CFAR algorithm in VHDL using real data with a window size of 13 by storing data in BRAM and using circular buffer mechanism. Currently looking for someone to make the project capable of processing complex data. Also need to make the window size variable in the range of 60-200