Block-Level RTL Design and Analysis
Budget: ₹100 – ₹400 INR
Seeking a proficient RTL design engineer to assist with a block-level design project. Your daily tasks will include Linting, CDC analysis, and Synthesis. Expertise is required in Verilog, the preferred hardware description language for this assignment.
Required Skills and Experience:
- Exceptional competence in RTL design
- Proven experience in Linting, CDC analysis, and Synthesis
- Proficiency in Verilog
- Experience in block-level design preferred
I look forward to collaborating with an engineer who will contribute valuable insight and expertise towards achieving the project objectives.
Required Skills and Experience:
- Exceptional competence in RTL design
- Proven experience in Linting, CDC analysis, and Synthesis
- Proficiency in Verilog
- Experience in block-level design preferred
I look forward to collaborating with an engineer who will contribute valuable insight and expertise towards achieving the project objectives.
Related categories:
Engineering
Electronics
Matlab and Mathematica
Verilog / VHDL
Electrical Engineering