Artix-7 High-Speed DAQ
Budget: $250 – $750 USD
I need a compact yet reliable data-acquisition design that runs on an Artix-7 FPGA and lets me capture analog signals up to about 50 MHz from 6 x AD9226 12 bit ADC's simultaneously . The goal is simple: store every sample intact to DDR3 for 500ms, and make the stored data available later by QSPI at 40MHz, or USART. Use one digital input as trigger to start AQ, one to erase full DDR3, one to select QSPI or USART.
Scope of work
• Build the RTL (VHDL or Verilog—your choice) that interfaces the FPGA with a suitable high-speed ADC, brings the samples into the fabric, and buffers them without loss.
• Implement a storage path—on-chip BRAM, external DDR3—to hold the data until I pull it off the board.
• Provide a clean, documented interface (for example QSPI, UART, USB FIFO) that I can use from a host PC or microcontroller to retrieve the stored data once acquisition stops.
• Include a simulation test-bench that proves the chain can handle a 50 MHz input, plus a brief user guide describing clocking, pinout expectations, and build steps in Vivado.
Acceptance criteria
1. Synthesis and implementation complete without timing violations on an Artix-7 speed-grade –2 device.
2. Simulation shows continuous capture of a 50 MHz sine wave for at least 500 ms with zero dropped samples.
3. After retrieval, the stored data reproduces the original waveform within the ADC’s resolution.
Hand-over items
– Synthesizable source files
– Test-bench and example waveform generator
– Vivado project (or command-line scripts)
– PDF/Markdown setup & usage notes
If you’ve tackled high-frequency analog acquisition on Xilinx parts before, this should feel familiar. Let’s make sure every sample is safe for later deep-dive analysis.
Scope of work
• Build the RTL (VHDL or Verilog—your choice) that interfaces the FPGA with a suitable high-speed ADC, brings the samples into the fabric, and buffers them without loss.
• Implement a storage path—on-chip BRAM, external DDR3—to hold the data until I pull it off the board.
• Provide a clean, documented interface (for example QSPI, UART, USB FIFO) that I can use from a host PC or microcontroller to retrieve the stored data once acquisition stops.
• Include a simulation test-bench that proves the chain can handle a 50 MHz input, plus a brief user guide describing clocking, pinout expectations, and build steps in Vivado.
Acceptance criteria
1. Synthesis and implementation complete without timing violations on an Artix-7 speed-grade –2 device.
2. Simulation shows continuous capture of a 50 MHz sine wave for at least 500 ms with zero dropped samples.
3. After retrieval, the stored data reproduces the original waveform within the ADC’s resolution.
Hand-over items
– Synthesizable source files
– Test-bench and example waveform generator
– Vivado project (or command-line scripts)
– PDF/Markdown setup & usage notes
If you’ve tackled high-frequency analog acquisition on Xilinx parts before, this should feel familiar. Let’s make sure every sample is safe for later deep-dive analysis.