ATS Resume for Physical Design Fresher -- 2
Budget: ₹600 – ₹1,500 INR
I need a ATS resume for fresher in Physical design and I had completed my Btech in Marri Laxman Reddy Institute of Technology and Management and Advance physical Design and Verification at MAven Silicons pvt. ltd banglore
my skills are Physical Design,Synthesis ,Floorplan , Placement , Clock Tree Synthesis , Routing , DFT , Physical Verification , Sign Off
Tools used: Fusion Compiler, Design Compiler, IC Compiler II, Calibre
Job Details
About the Role:
We are looking for a skilled Physical Design Engineer to join our VLSI design team. You will be responsible for implementing digital designs into physical layouts, ensuring optimal performance, area, and power consumption, while meeting timing constraints. This role requires strong expertise in EDA tools and a deep understanding of the entire physical design flow from RTL to GDSII.
Key Responsibilities:
Perform floorplanning, placement, and routing of digital designs.
Manage clock tree synthesis (CTS), power planning, and timing closure.
Run and analyze physical verification checks (DRC, LVS, ERC).
Work closely with front-end design teams for timing constraints and logic equivalence.
Optimize power, performance, and area (PPA) metrics.
Debug issues related to signal integrity, electromigration, and IR drop analysis.
Develop and maintain scripts for automation (TCL, Perl, Python).
Required Qualifications:
Bachelor’s/Master’s degree in Electrical Engineering, Electronics, or a related field.
[X]+ years of experience in physical design and ASIC/SoC development.
Strong experience with EDA tools (Cadence Innovus, Synopsys ICC2, Mentor Graphics).
Proficiency in scripting languages (TCL, Python, Perl) for automation.
Solid understanding of STA (Static Timing Analysis), DFT (Design for Testability), and low-power design techniques.
Preferred Qualifications:
Experience with advanced process nodes (e.g., 5nm, 7nm, or below).
Knowledge of chip-package co-design and thermal analysis.
Strong analytical and problem-solving skills.
I will give $10 for this resume
my skills are Physical Design,Synthesis ,Floorplan , Placement , Clock Tree Synthesis , Routing , DFT , Physical Verification , Sign Off
Tools used: Fusion Compiler, Design Compiler, IC Compiler II, Calibre
Job Details
About the Role:
We are looking for a skilled Physical Design Engineer to join our VLSI design team. You will be responsible for implementing digital designs into physical layouts, ensuring optimal performance, area, and power consumption, while meeting timing constraints. This role requires strong expertise in EDA tools and a deep understanding of the entire physical design flow from RTL to GDSII.
Key Responsibilities:
Perform floorplanning, placement, and routing of digital designs.
Manage clock tree synthesis (CTS), power planning, and timing closure.
Run and analyze physical verification checks (DRC, LVS, ERC).
Work closely with front-end design teams for timing constraints and logic equivalence.
Optimize power, performance, and area (PPA) metrics.
Debug issues related to signal integrity, electromigration, and IR drop analysis.
Develop and maintain scripts for automation (TCL, Perl, Python).
Required Qualifications:
Bachelor’s/Master’s degree in Electrical Engineering, Electronics, or a related field.
[X]+ years of experience in physical design and ASIC/SoC development.
Strong experience with EDA tools (Cadence Innovus, Synopsys ICC2, Mentor Graphics).
Proficiency in scripting languages (TCL, Python, Perl) for automation.
Solid understanding of STA (Static Timing Analysis), DFT (Design for Testability), and low-power design techniques.
Preferred Qualifications:
Experience with advanced process nodes (e.g., 5nm, 7nm, or below).
Knowledge of chip-package co-design and thermal analysis.
Strong analytical and problem-solving skills.
I will give $10 for this resume