ASIC Performance Optimization via Fusion Compiler(synthesis)
Budget: ₹750 – ₹1,250 INR
I'm seeking an expert in ASIC synthesis utilizing the Fusion Compiler tool. The primary objective of this project is to optimize the performance of a custom logic digital design written in Verilog.
Key Responsibilities:
- Conduct synthesis of a custom logic design for optimizing performance.
- Employ the Fusion Compiler tool for this task.
- Deliver the project with a high level of precision and attention to detail.
Ideal Skills and Experience:
- Extensive experience with ASIC synthesis.
- Proficiency in the Fusion Compiler tool.
- Strong background in custom logic design.
- In-depth knowledge of Verilog.
- Excellent performance optimization skills.
Key Responsibilities:
- Conduct synthesis of a custom logic design for optimizing performance.
- Employ the Fusion Compiler tool for this task.
- Deliver the project with a high level of precision and attention to detail.
Ideal Skills and Experience:
- Extensive experience with ASIC synthesis.
- Proficiency in the Fusion Compiler tool.
- Strong background in custom logic design.
- In-depth knowledge of Verilog.
- Excellent performance optimization skills.