KiCad Industrial Control PCB Design
Budget: $250 – $750 USD
CAD: KiCad v9
Stack-up: 4-layer minimum (Signal / GND / Power / Signal). Use 6-layer only if routing/thermal demands.
Temp rating: Operate −40…+105 °C (select 125 °C parts for hot sections: AO power, DC/DC, DO drivers).
Form: One Main Controller board + external SSR Board(s) (plug-and-play). Designer to propose board size and connector strategy.
1) Main Controller Board – Electronics
MCU & Communications
• MCU: STM32H753 (H743 footprint fallback), 25 MHz HSE + LSE, SWD, BOOT/recovery jumpers.
• Ethernet: DP83848 (RMII), RJ45 + magnetics, ESD/CM choke, link/ACT LEDs.
• RS-485 / RS-232: isolated transceivers, TVS, DE/RE signal to MCU.
Power
• Input 24 VDC (18–32 V), reverse-polarity + surge/EFT protection.
• On-board rails: 5 V and 3.3 V DC/DC; isolated rails where needed (AI active loops, HART coupling as required).
Analog Inputs — 6 × 4–20 mA
• Burden: 249–250 Ω ±0.1 % (≤25 ppm/°C), ≥0.25 W, Kelvin sense to ADC.
• Front-end: RC anti-alias (≈100 Ω + 1 µF), input clamps + TVS to AGND.
• ADC: ADS1115-class (I²C, address straps).
• Modes per channel:
o Passive (externally powered transmitter).
o Active (board-supplied isolated 24 V loop via polyfuse 100–150 mA).
• Connector: 2-pin per channel (AI+ / AI−).
Analog Outputs — 6 × 4–20 mA (Active & Passive) with HART
• Core IC: DAC8775 (QFN-72) or Similar DAC with 8 channels.
• Ranges: 4–20 mA (default), jumperable 0–20 mA.
• Compliance: Must drive 20 mA into ≥600 Ω @ 24 V.
• HART (Mandatory):
o AD5700 (or equivalent) per channel + coupling network; HART IN/OUT test pad per channel; keep analog/RF layout guidance.
• Protection: Output TVS to GND, series PTC (60–120 mA), optional RC snubber for long cable.
• Modes (silk clearly marked):
o AO-Active: board sources loop (24 V).
o AO-Passive: external 24 V supplies loop; board regulates current only.
• Test pads: IOUT / RTN / HART clip points.
Temperature Inputs
• RTD: up to 10 × Pt100 via MAX31865, SPI Mode-3, per-channel /CS, 2, 3/4-wire select via jumpers, bias + 50/60 Hz filter controllable.
• Thermocouple: 1 × K-type via MAX31856 (SPI) with CJ compensation; RC + TVS at input; TC terminal in isothermal area.
Digital Outputs — 24 total
• 18 × Standard 24 V DO (on Main board):
o Low-side N-MOSFET (≥0.5 A/ch), per-channel flyback (for coils), DO rail TVS, status LED per channel, grouped field terminals.
• 6 × “SSR Control Ports” (on Main board):
o Purpose: Drive external AC SSR board(s) (25 A @ 110/230 VAC) in plug-and-play fashion.
o Per-port electrical spec:
CTRL+ (24 V) / CTRL− (0 V): 3–15 mA drive (to light SSR board’s opto/driver input).
+24V_OUT (fused 100–150 mA) to power SSR board control side.
FAULT_FB (open-collector/optocoupled return from SSR board; pulled up on Main board to 3.3 V).
o Recommended 4-pin keyed locking header per channel (per SSR port):
Pin-1: +24V_OUT, Pin-2: CTRL+, Pin-3: CTRL− (0 V), Pin-4: FAULT_FB.
o Cable/Harness: 4-wire, shielded option; label both ends (SSR#1…SSR#6).
o Notes: These six ports do NOT switch mains on the Main board—they only command/monitor the external SSR boards.
Digital Inputs — 4 × 24 V dry contact
• Opto/protected input stage, RC debounce, LED per channel.
Grounding/Partitioning
• Split AGND/DGND, single-point star tie.
• Physical zones: High-energy (away from analog), Analog, Digital/MCU, ETH corner with controlled impedance.
________________________________________
2) External SSR Board(s) – Plug-and-Play
The SSR function is off-board to simplify thermal & safety and to keep Main board compact.
Function: Each SSR board switches 1× AC load up to 25 A @ 110/230 VAC using back-to-back MOSFETs with an isolated gate driver, and exposes a fault/status back to the Main board.
Electrical / Protection
• Input (from Main board SSR Port): +24V, CTRL+, CTRL−, FAULT_FB return (optocoupled).
• AC Power Path: B2B MOSFETs, device choice sized for 25 A continuous (resistive), with thermal margin; bolt-on heatsink area.
• Protections:
o Bidirectional TVS across AC path sized so V_BR > Vac_peak and V_C < MOSFET V_DS(max).
o RC snubber across AC nodes to control dv/dt and prevent re-trigger.
o OCP via shunt + driver threshold; OTP via NTC/thermal sense → FAULT_FB latch to Main board.
o MOV at panel mains entry (panel-level item).
• I/O:
o AC_IN / AC_OUT high-current terminals (≥25 A rating).
o Low-voltage 4-pin header to Main board (keyed, locking).
• Safety: Creepage/clearance for 250 VAC, isolation barrier to LV section, slotting where needed, red HV keep-outs, warning silks.
• Mechanical: Heatsink mounting holes, airflow notes; board outline to fit DIN-rail or panel plate.
• Status LED(s): Power, ON, FAULT.
________________________________________
3) Layout & Mechanical (Main board)
• Impedance: 100 Ω diff for ETH pairs; short, symmetric routes; magnetics near RJ45.
• Analog care: Kelvin sense on AI burdens; guard rings at precision nodes; short RTD/TC sense loops.
• Thermal: Copper pours + via arrays under DC/DCs, DAC8775 power area; keep high-energy DO and SSR ports far from analog.
• Connectors:
o 2-pin per AI, 2-pin per AO loop, grouped DO 24 V terminals, six 4-pin SSR control headers (keyed), RTD/TC headers.
• Mounting: Standoffs; allow enclosure/din options; clear silk labels for AI/AO Active/Passive and SSR Ports.
________________________________________
4) Deliverables (Design-Only)
1. KiCad v9 project (schematics, PCB, custom libs, 3D STEP).
2. Gerbers + drills + fab notes + stack-up (DFM-ready).
3. Assembly pack: Pick-and-Place CSV + assembly drawings/renders.
4. BOM: MPNs + alternates; include temp/voltage ratings.
5. Pin/Connector Map: CSV + annotated PDF (include SSR port pinout and harness diagram).
6. Minimal calcs (notes page):
o AO compliance proof (20 mA into 600 Ω @ 24 V).
o SSR board device/TVS/snubber sizing summary (no lab validation).
________________________________________
5) Acceptance (no lab testing phase)
• ERC/DRC clean; netlist/BOM consistent; ETH impedance rules set.
• Clear silk and connector legends for AI/AO Active/Passive and SSR Ports.
• Mechanical/thermal provisions defined for SSR external solution (heatsink holes, current widths on SSR board).
• Documentation sufficient for fabrication and assembly without ambiguity.
Stack-up: 4-layer minimum (Signal / GND / Power / Signal). Use 6-layer only if routing/thermal demands.
Temp rating: Operate −40…+105 °C (select 125 °C parts for hot sections: AO power, DC/DC, DO drivers).
Form: One Main Controller board + external SSR Board(s) (plug-and-play). Designer to propose board size and connector strategy.
1) Main Controller Board – Electronics
MCU & Communications
• MCU: STM32H753 (H743 footprint fallback), 25 MHz HSE + LSE, SWD, BOOT/recovery jumpers.
• Ethernet: DP83848 (RMII), RJ45 + magnetics, ESD/CM choke, link/ACT LEDs.
• RS-485 / RS-232: isolated transceivers, TVS, DE/RE signal to MCU.
Power
• Input 24 VDC (18–32 V), reverse-polarity + surge/EFT protection.
• On-board rails: 5 V and 3.3 V DC/DC; isolated rails where needed (AI active loops, HART coupling as required).
Analog Inputs — 6 × 4–20 mA
• Burden: 249–250 Ω ±0.1 % (≤25 ppm/°C), ≥0.25 W, Kelvin sense to ADC.
• Front-end: RC anti-alias (≈100 Ω + 1 µF), input clamps + TVS to AGND.
• ADC: ADS1115-class (I²C, address straps).
• Modes per channel:
o Passive (externally powered transmitter).
o Active (board-supplied isolated 24 V loop via polyfuse 100–150 mA).
• Connector: 2-pin per channel (AI+ / AI−).
Analog Outputs — 6 × 4–20 mA (Active & Passive) with HART
• Core IC: DAC8775 (QFN-72) or Similar DAC with 8 channels.
• Ranges: 4–20 mA (default), jumperable 0–20 mA.
• Compliance: Must drive 20 mA into ≥600 Ω @ 24 V.
• HART (Mandatory):
o AD5700 (or equivalent) per channel + coupling network; HART IN/OUT test pad per channel; keep analog/RF layout guidance.
• Protection: Output TVS to GND, series PTC (60–120 mA), optional RC snubber for long cable.
• Modes (silk clearly marked):
o AO-Active: board sources loop (24 V).
o AO-Passive: external 24 V supplies loop; board regulates current only.
• Test pads: IOUT / RTN / HART clip points.
Temperature Inputs
• RTD: up to 10 × Pt100 via MAX31865, SPI Mode-3, per-channel /CS, 2, 3/4-wire select via jumpers, bias + 50/60 Hz filter controllable.
• Thermocouple: 1 × K-type via MAX31856 (SPI) with CJ compensation; RC + TVS at input; TC terminal in isothermal area.
Digital Outputs — 24 total
• 18 × Standard 24 V DO (on Main board):
o Low-side N-MOSFET (≥0.5 A/ch), per-channel flyback (for coils), DO rail TVS, status LED per channel, grouped field terminals.
• 6 × “SSR Control Ports” (on Main board):
o Purpose: Drive external AC SSR board(s) (25 A @ 110/230 VAC) in plug-and-play fashion.
o Per-port electrical spec:
CTRL+ (24 V) / CTRL− (0 V): 3–15 mA drive (to light SSR board’s opto/driver input).
+24V_OUT (fused 100–150 mA) to power SSR board control side.
FAULT_FB (open-collector/optocoupled return from SSR board; pulled up on Main board to 3.3 V).
o Recommended 4-pin keyed locking header per channel (per SSR port):
Pin-1: +24V_OUT, Pin-2: CTRL+, Pin-3: CTRL− (0 V), Pin-4: FAULT_FB.
o Cable/Harness: 4-wire, shielded option; label both ends (SSR#1…SSR#6).
o Notes: These six ports do NOT switch mains on the Main board—they only command/monitor the external SSR boards.
Digital Inputs — 4 × 24 V dry contact
• Opto/protected input stage, RC debounce, LED per channel.
Grounding/Partitioning
• Split AGND/DGND, single-point star tie.
• Physical zones: High-energy (away from analog), Analog, Digital/MCU, ETH corner with controlled impedance.
________________________________________
2) External SSR Board(s) – Plug-and-Play
The SSR function is off-board to simplify thermal & safety and to keep Main board compact.
Function: Each SSR board switches 1× AC load up to 25 A @ 110/230 VAC using back-to-back MOSFETs with an isolated gate driver, and exposes a fault/status back to the Main board.
Electrical / Protection
• Input (from Main board SSR Port): +24V, CTRL+, CTRL−, FAULT_FB return (optocoupled).
• AC Power Path: B2B MOSFETs, device choice sized for 25 A continuous (resistive), with thermal margin; bolt-on heatsink area.
• Protections:
o Bidirectional TVS across AC path sized so V_BR > Vac_peak and V_C < MOSFET V_DS(max).
o RC snubber across AC nodes to control dv/dt and prevent re-trigger.
o OCP via shunt + driver threshold; OTP via NTC/thermal sense → FAULT_FB latch to Main board.
o MOV at panel mains entry (panel-level item).
• I/O:
o AC_IN / AC_OUT high-current terminals (≥25 A rating).
o Low-voltage 4-pin header to Main board (keyed, locking).
• Safety: Creepage/clearance for 250 VAC, isolation barrier to LV section, slotting where needed, red HV keep-outs, warning silks.
• Mechanical: Heatsink mounting holes, airflow notes; board outline to fit DIN-rail or panel plate.
• Status LED(s): Power, ON, FAULT.
________________________________________
3) Layout & Mechanical (Main board)
• Impedance: 100 Ω diff for ETH pairs; short, symmetric routes; magnetics near RJ45.
• Analog care: Kelvin sense on AI burdens; guard rings at precision nodes; short RTD/TC sense loops.
• Thermal: Copper pours + via arrays under DC/DCs, DAC8775 power area; keep high-energy DO and SSR ports far from analog.
• Connectors:
o 2-pin per AI, 2-pin per AO loop, grouped DO 24 V terminals, six 4-pin SSR control headers (keyed), RTD/TC headers.
• Mounting: Standoffs; allow enclosure/din options; clear silk labels for AI/AO Active/Passive and SSR Ports.
________________________________________
4) Deliverables (Design-Only)
1. KiCad v9 project (schematics, PCB, custom libs, 3D STEP).
2. Gerbers + drills + fab notes + stack-up (DFM-ready).
3. Assembly pack: Pick-and-Place CSV + assembly drawings/renders.
4. BOM: MPNs + alternates; include temp/voltage ratings.
5. Pin/Connector Map: CSV + annotated PDF (include SSR port pinout and harness diagram).
6. Minimal calcs (notes page):
o AO compliance proof (20 mA into 600 Ω @ 24 V).
o SSR board device/TVS/snubber sizing summary (no lab validation).
________________________________________
5) Acceptance (no lab testing phase)
• ERC/DRC clean; netlist/BOM consistent; ETH impedance rules set.
• Clear silk and connector legends for AI/AO Active/Passive and SSR Ports.
• Mechanical/thermal provisions defined for SSR external solution (heatsink holes, current widths on SSR board).
• Documentation sufficient for fabrication and assembly without ambiguity.