Simulator for Out-of-Order Processor supporting speculative execution using register renaming

Involves the implementation of a simulator for an out-of-order processor that supports speculative execution using register renaming. The processor follows an APEX-like ISA (Instruction Set Architecture) and includes components such as an issue queue (IQ), load-store queue (LSQ), reorder buffer (ROB), and a branch target buffer (BTB). The ISA includes instructions for arithmetic and logical operations, memory accesses, conditional branching, control transfers, and more.