Design a memory hierarchy

Our goal is to design a memory hierarchy for a pipelined processor that includes 2 levels of cache and satisfies five design criteria. The only instructions that read data from or write data to memory are loads (15% of all instructions) and stores (10% of all instructions).

Criterion 1- Total AMAT of our multi-level Cache < 9CC
Criterion 2- Total MissRate of our multi-level Cache < 7%
Criterion 3- We want our L2 cache to be inclusive. You are given options to organize your hierarchy:
Option 1: uses a split L1 cache and a split L2 cache (effectively 4 caches are used).
Option 2: uses a split L1 cache, but a unified L2 cache (effectively 3 caches are used).
Option 3: uses a unified L1 cache and a unified L2 cache (effectively 2 caches are used).

Criterion 4- Due to cost constraints, the total capacity of all caches you use in your design should be < 400 KB.
Criterion 5- Three type of Caches are available (more than one of each type can be used in your design, as long as criteria 1-4 are satisfied). You can use these as a 1) unified cache or 2) as a data cache or instruction cache in a split format. The specs below are only valid when the hierarchy satisfies the size constraint: caches close to processor are smaller than caches close to main memory.
Small Cache:
• Capacity = 64 KB
• HTL1(HittimeifusedinL1)=1CC
• HTL2=5CC
• MRL1 = 10%
• MRL2 = 90%
Medium Cache:
• Capacity = 128 KB
• HTL1=1CC
• HTL2=5CC
• MRL1 = 6%
• MRL2 = 60%

Large Cache
• Capacity = 256 KB
• HTL1=1CC
• HTL2=20CC
• MRL1 = 2%
• MRL2 = 50%

Other important notes:
• Miss Penalty (MP) of accessing man memory (Main Memory access latency) is 100 CC
• Assume that all caches use a write-back policy, and 30% of evicted data is dirty
• If it is impossible to satisfy the criteria above, select the design that satisfies most of
the criteria and has the closest solution to the criterion that it does not satisfy.


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