32 bit CLA Adder in Cadence Virtuoso
Budget: ₹5,000 – ₹10,000 INR
Implementation: we will implement 32 bit CLA adder in cadence virtuoso with transient analysis along with mos count, power consumption and delay values along with low power technique to reduce the parameter.Its an extension of 16bit CLA Adder.
Tool: Cadence virtuoso
Deliverables: RTL code
Test Benchs
Simulation Results
Synthesis Report
Timing Analysis
Well written documentation
Paper for publication
Tool: Cadence virtuoso
Deliverables: RTL code
Test Benchs
Simulation Results
Synthesis Report
Timing Analysis
Well written documentation
Paper for publication