KiCad DRL Circuit Analysis, fix and simulation
Budget: €20 – €40 EUR
I am looking for an experienced electronics engineer to review, validate, and improve a Driven Right Leg (DRL) circuit designed in KiCad. The circuit is part of an Arduino-based EEG front-end, where the DRL is used to reduce common-mode noise (mainly 50 Hz mains interference in Europe) and improve signal quality.
The freelancer must analyze the existing schematic, evaluate the DRL loop stability, feedback design, and overall effectiveness in common-mode noise rejection. If needed, the circuit should be corrected and optimized by adjusting component values or modifying the topology.
A key requirement is both mathematical analysis and simulation-based validation. The freelancer must explain the circuit operation using equations and demonstrate its performance through simulation (LTSpice or similar).
The simulation must clearly show reduction of common-mode noise (e.g. 50 Hz), comparison with and without DRL, stable behavior (no oscillations), and improvement of the signal quality. The analysis must not be limited to a single frequency; the circuit should also be evaluated over a wider frequency range to ensure robustness against harmonics and broadband noise.
For realistic results, it is strongly recommended to include a simplified body model (RC network for electrode/body impedance) in the simulation.
The final deliverables should include the corrected schematic (or documented changes), simulation files, graphs, and a short technical explanation of the improvements and results.
Only proposals that include both simulation and mathematical analysis/justification will be considered.
The freelancer must analyze the existing schematic, evaluate the DRL loop stability, feedback design, and overall effectiveness in common-mode noise rejection. If needed, the circuit should be corrected and optimized by adjusting component values or modifying the topology.
A key requirement is both mathematical analysis and simulation-based validation. The freelancer must explain the circuit operation using equations and demonstrate its performance through simulation (LTSpice or similar).
The simulation must clearly show reduction of common-mode noise (e.g. 50 Hz), comparison with and without DRL, stable behavior (no oscillations), and improvement of the signal quality. The analysis must not be limited to a single frequency; the circuit should also be evaluated over a wider frequency range to ensure robustness against harmonics and broadband noise.
For realistic results, it is strongly recommended to include a simplified body model (RC network for electrode/body impedance) in the simulation.
The final deliverables should include the corrected schematic (or documented changes), simulation files, graphs, and a short technical explanation of the improvements and results.
Only proposals that include both simulation and mathematical analysis/justification will be considered.