28 GHz RF downconverter with IF 5-6Ghz

I have a working schematic for a double-balanced Gilbert mixer aimed at 28 GHz in a 65 / 60 nm CMOS flow on Cadence Virtuoso (ADE L/XL). The core blocks—RF matching network, current-commutating mixer pair and preliminary LO frequency doubler—are in place, but they still sit at pre-layout, simulation-only level. My priority now is to turn this into a tape-out-ready design that meets the targets below once post-layout parasitics are included.

Key electrical goals
• RF = 28 GHz, LO = 26.4 GHz, IF = 1.6 GHz
• Conversion gain better than ‑3 dB (-2.32 dB target)
• s11 < ‑10 dB at 28 GHz
• VDD = 2.4 V

Most of the heavy lifting will be on overall system integration—getting the RF input match, LO doubler chain, switching quad and IF output stage to behave as one clean path. The LO network in particular shows noticeable signal-integrity degradation that needs to be ironed out before any layout starts.

What I need from you
1. Audit existing Cadence schematics, models and Spectre-RF benches.
2. Refine biasing, device sizing and passive networks so each spec is achieved with margin.
3. Close the loop on the LO doubler: improve phase noise, limit feed-through and cure present integrity issues.
4.Most important is I need all important analysis of the design.
5. Deliver a clean, hierarchical schematic set, corner-sim results (process / voltage / temperature), and a brief report summarising decisions and trade-offs.


Please attach examples of past Ka-/mm-wave or mixer work you have taken to silicon; those references will weigh most in my selection.