Computer architecture SimpleScalar simulator

you will be asked to use the SimpleScalar “sim-outorder” model and the
SPEC 2000 benchmark suite to evaluate the performance impact of a number of basic cache
configuration parameters, such as the L1 and L2 cache size, associativity, block size, and so on.
The following is a list of example configurations you can start with, you are not required to exactly
follow them, and you are free to think out and try any configuration you would like to test. Actually,
if you can try some other configurations besides the following ones, I will give you some bonus on
your project.
a) Instruction cache size (compare 8KB, 32 KB and 64KB, block size and associativity follow the
default configuration)
b) Data cache size (compare 2KB, 32KB, and 128KB, all 4-way set associative, block size follow the
default configuration )
c) Data cache associativity (compare 1-way, 2-way, 8-way, all 32KB, block size follow the default
configuration)
d)L2 cache size (compare 128KB, 512KB, and 1MB, block size and associativity follow the default
configuration)
e)L1 and L2 block size (compare 32B, 64B, 128B, and 256B, cache size and associativity follow
the default configuration)
You are suggested to run the simulator using the default parameters except for the parameters
under study to better evaluate the impact of the configurations on the performance. You are
suggested to run each SPEC2000 benchmark for 100 million instructions after skipping 100
million instructions. Note: skipping a large number of instructions is quite important to warm up the
cache, and run a relatively large number of instructions is important to get more accurate results.
The results should be compared by using the number of instructions per cycle (IPC), cache miss
rate, the number of load/store instructions, and any other useful information you can obtain from
the simulator outputs for the executed program.