Custom Signal-Processing CPU on FPGA
Budget: $10 – $30 AUD
I’m pushing a fast-turnaround project and need another pair of expert hands. The goal is a small, custom CPU core—built purely in Verilog or VHDL—tuned for signal-processing tasks and proven on a Xilinx board you already have running on your bench.
I’ll supply the high-level instruction set, throughput targets, and the specific signal operations I need accelerated. You’ll translate that into a synthesizable design, simulate it, meet timing, and show it running on your board so we can iterate in real time.
Deliverables
• RTL source (Verilog or VHDL)
• Simulation test-bench with passing waveforms
• Synthesized design for a recent Xilinx family (Vivado project or equivalent)
• Resource and timing report hitting the agreed clock rate
• Short demo video or live call showing the core executing my test vectors on your hardware
If you’re comfortable crafting custom datapaths, optimizing for DSP slices, and can turn this around quickly, let’s get started today.
I’ll supply the high-level instruction set, throughput targets, and the specific signal operations I need accelerated. You’ll translate that into a synthesizable design, simulate it, meet timing, and show it running on your board so we can iterate in real time.
Deliverables
• RTL source (Verilog or VHDL)
• Simulation test-bench with passing waveforms
• Synthesized design for a recent Xilinx family (Vivado project or equivalent)
• Resource and timing report hitting the agreed clock rate
• Short demo video or live call showing the core executing my test vectors on your hardware
If you’re comfortable crafting custom datapaths, optimizing for DSP slices, and can turn this around quickly, let’s get started today.