Compact Driver Stage Design for Teensy 4.1
Budget: €30 – €250 EUR
500mA output injected into the power line This is a workspace for: I have a Teensy 4.1 producing a 0–3.3 V, 80 kHz square wave that must be pushed onto a power line as a clean ±3 V logic-level signal. The link sits inside an industrial-automation cabinet that is notoriously high in conducted and radiated noise, so frequency stability, pristine edges, tight duty-cycle fidelity, and minimal added jitter are non-negotiable.
The line is already carrying both analogue sensing and digital control, so I need a compact driver stage that:
• Takes the Teensy’s 3.3 V CMOS output.
• Runs from the existing 12 V rail.
• Delivers a symmetrical ±3 V square wave at 80 kHz with crisp transitions—no ringing or overshoot.
• Preserves the original duty cycle and timing accuracy.
• Maintains strong immunity against the cabinet’s electrical noise; I am currently leaning on well-chosen low-pass filtering for extra protection.
You are free to choose the most suitable topology—discrete, op-amp based, transformer coupled, or otherwise—as long as component availability is good and the final solution remains compact. Please provide:
1. Schematic with full component values.
2. Brief design notes explaining how edge integrity, jitter, and noise rejection targets are met.
3. Optional PCB layout (KiCad preferred) if this can be done quickly.
4. Bill of materials with supplier part numbers.
I’ll test the stage on a scope and spectrum analyser; acceptance hinges on seeing a stable ±3.0 V ±5 % swing at 80 kHz with rise/fall times below 100 ns and less than 1 % added jitter.
The line is already carrying both analogue sensing and digital control, so I need a compact driver stage that:
• Takes the Teensy’s 3.3 V CMOS output.
• Runs from the existing 12 V rail.
• Delivers a symmetrical ±3 V square wave at 80 kHz with crisp transitions—no ringing or overshoot.
• Preserves the original duty cycle and timing accuracy.
• Maintains strong immunity against the cabinet’s electrical noise; I am currently leaning on well-chosen low-pass filtering for extra protection.
You are free to choose the most suitable topology—discrete, op-amp based, transformer coupled, or otherwise—as long as component availability is good and the final solution remains compact. Please provide:
1. Schematic with full component values.
2. Brief design notes explaining how edge integrity, jitter, and noise rejection targets are met.
3. Optional PCB layout (KiCad preferred) if this can be done quickly.
4. Bill of materials with supplier part numbers.
I’ll test the stage on a scope and spectrum analyser; acceptance hinges on seeing a stable ±3.0 V ±5 % swing at 80 kHz with rise/fall times below 100 ns and less than 1 % added jitter.