Semiconductor Design Team Recruitment
Budget: ₹150,000 – ₹250,000 INR
I am assembling a 30-member core team to take India from “importer” to “exporter” of advanced computing-grade semiconductor chipsets. Our immediate mandate is chip design and architecture that can scale from laptops through high-performance desktops, with a longer-term roadmap toward mobile and household appliance variants.
Scope & objectives
• Complete front-to-back architecture, RTL, verification, physical design and tape-out readiness for a flagship computing SoC.
• Establish robust embedded-Linux–based reference boards and SDKs.
• Lay the process groundwork for future fabrication partnerships outside India while we lobby for domestic fabs.
Why this is different
The programme is already capitalised at ₹55 crore, earmarked for salaries, EDA licences, prototype runs and bonus pools tied to tape-out milestones. Your compensation is therefore predictable and performance-linked rather than speculative.
Roles we still need to fill (4+ yrs exp each)
System architects, embedded and systems programmers, verification engineers, physical design specialists, DevOps for CI/CD of RTL builds, HR lead for technical hiring, tech managers and team leads. Solid command of SystemVerilog/VHDL, C/C++, Linux kernel or Yocto, scripting, and modern EDA toolchains (Synopsys, Cadence, Siemens) is expected.
What to include in your application
Show me clear evidence of relevant experience—projects you’ve taken from spec to silicon or to FPGA prototypes, particularly for computing devices. Mention any industry connections (fabs, EDA vendors, IP houses) you can bring; they matter.
Key acceptance criteria
• Architecture spec frozen within 60 days of team formation
• First FPGA bring-up by month 6
• Tape-out-ready GDSII no later than month 12
If you’re passionate about putting India on the global semiconductor map and ready to own a slice of this ambitious timeline, let’s talk.
Scope & objectives
• Complete front-to-back architecture, RTL, verification, physical design and tape-out readiness for a flagship computing SoC.
• Establish robust embedded-Linux–based reference boards and SDKs.
• Lay the process groundwork for future fabrication partnerships outside India while we lobby for domestic fabs.
Why this is different
The programme is already capitalised at ₹55 crore, earmarked for salaries, EDA licences, prototype runs and bonus pools tied to tape-out milestones. Your compensation is therefore predictable and performance-linked rather than speculative.
Roles we still need to fill (4+ yrs exp each)
System architects, embedded and systems programmers, verification engineers, physical design specialists, DevOps for CI/CD of RTL builds, HR lead for technical hiring, tech managers and team leads. Solid command of SystemVerilog/VHDL, C/C++, Linux kernel or Yocto, scripting, and modern EDA toolchains (Synopsys, Cadence, Siemens) is expected.
What to include in your application
Show me clear evidence of relevant experience—projects you’ve taken from spec to silicon or to FPGA prototypes, particularly for computing devices. Mention any industry connections (fabs, EDA vendors, IP houses) you can bring; they matter.
Key acceptance criteria
• Architecture spec frozen within 60 days of team formation
• First FPGA bring-up by month 6
• Tape-out-ready GDSII no later than month 12
If you’re passionate about putting India on the global semiconductor map and ready to own a slice of this ambitious timeline, let’s talk.