Optimization of Negative capacitance Vertical-Tunnel Fet(NCVT-FET) TCAD Simulation
Budget: ₹1,000 – ₹2,500 INR
Project Title: Optimization of Negative-Capacitance Vertical-Tunnel FET (NCVT-FET)
Objective:
The goal of this project is to optimize the design of Negative-Capacitance Vertical-Tunnel FET (NCVT-FET) using GaAsSb/InGaAs material. The focus is on maximizing vertical tunneling and minimizing corner tunneling to achieve higher ON-current (ION) and lower subthreshold swing (SS), making it suitable for ultra-low power applications like IoT and wearables.
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Key Areas of Optimization:
1. Gate-to-Source Overlap (Lsov):
Increasing Lsov enhances vertical tunneling, leading to a higher ON-current (ION).
2. Tunnel Layer Thickness (Tt):
Optimizing Tt is crucial to balance tunneling efficiency and electric field strength.
3. Doping Concentration in Tunnel Layer:
Selective N++ doping enhances vertical tunneling while suppressing unwanted leakage.
4. Ferroelectric (FE) Layer Properties:
Adjusting thickness (Tfe) and coercive field (Ec) improves the negative capacitance effect, reducing subthreshold swing (SS) and boosting performance.
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Expected Performance Goals:
ION = 405 μA/μm, IOFF = 10 pA/μm at VDD = 0.5V.
Subthreshold Swing (SS) = 14 mV/dec over 4 decades of current.
144× higher ION at VDD = 0.1V compared to a standard TFET.
ION/IOFF ratio of 6 × 10⁵ for ultra-low power operation.
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Project Scope:
1. Device Modeling & Simulation:
Use TCAD tools to simulate and optimize NCVT-FET structures.
Implement nonlocal charge carrier tunneling and Landau–Khalatnikov equations for ferroelectric effects.
2. Parameter Optimization:
Fine-tune Lsov, Tt, doping concentration, and FE layer properties to improve device performance.
3. Performance Analysis:
Compare NCVT-FET vs. TFET in terms of ION, IOFF, SS, and power efficiency.
Investigate the impact of random dopant fluctuations (RDF) and thickness variations.
4. Deliverables:
Optimized device structure files.
Simulation reports with comparative analysis.
Graphical plots of IDS–VGS, SS, and tunneling efficiency.
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Ideal:
Expertise in Semiconductor Device Physics
Experience with TCAD Simulations (Synopsys Sentaurus, Silvaco, or similar)
Understanding of Ferroelectric Materials and Negative Capacitance
Strong Analytical and Report Writing Skills
This project will contribute to ultra-low power transistor design, which is critical for next-generation electronics.
Objective:
The goal of this project is to optimize the design of Negative-Capacitance Vertical-Tunnel FET (NCVT-FET) using GaAsSb/InGaAs material. The focus is on maximizing vertical tunneling and minimizing corner tunneling to achieve higher ON-current (ION) and lower subthreshold swing (SS), making it suitable for ultra-low power applications like IoT and wearables.
---
Key Areas of Optimization:
1. Gate-to-Source Overlap (Lsov):
Increasing Lsov enhances vertical tunneling, leading to a higher ON-current (ION).
2. Tunnel Layer Thickness (Tt):
Optimizing Tt is crucial to balance tunneling efficiency and electric field strength.
3. Doping Concentration in Tunnel Layer:
Selective N++ doping enhances vertical tunneling while suppressing unwanted leakage.
4. Ferroelectric (FE) Layer Properties:
Adjusting thickness (Tfe) and coercive field (Ec) improves the negative capacitance effect, reducing subthreshold swing (SS) and boosting performance.
---
Expected Performance Goals:
ION = 405 μA/μm, IOFF = 10 pA/μm at VDD = 0.5V.
Subthreshold Swing (SS) = 14 mV/dec over 4 decades of current.
144× higher ION at VDD = 0.1V compared to a standard TFET.
ION/IOFF ratio of 6 × 10⁵ for ultra-low power operation.
---
Project Scope:
1. Device Modeling & Simulation:
Use TCAD tools to simulate and optimize NCVT-FET structures.
Implement nonlocal charge carrier tunneling and Landau–Khalatnikov equations for ferroelectric effects.
2. Parameter Optimization:
Fine-tune Lsov, Tt, doping concentration, and FE layer properties to improve device performance.
3. Performance Analysis:
Compare NCVT-FET vs. TFET in terms of ION, IOFF, SS, and power efficiency.
Investigate the impact of random dopant fluctuations (RDF) and thickness variations.
4. Deliverables:
Optimized device structure files.
Simulation reports with comparative analysis.
Graphical plots of IDS–VGS, SS, and tunneling efficiency.
---
Ideal:
Expertise in Semiconductor Device Physics
Experience with TCAD Simulations (Synopsys Sentaurus, Silvaco, or similar)
Understanding of Ferroelectric Materials and Negative Capacitance
Strong Analytical and Report Writing Skills
This project will contribute to ultra-low power transistor design, which is critical for next-generation electronics.