Create TB Components of PCIe Physical Layer ( Logical) Testbench Components
Budget: ₹12,500 – ₹37,500 INR
Job Description :-
Development of PCIe Logical Physical Layer Testbench Components :-
1) Go through PCIE gen 5 spec, existing TB Architecture by both reading and discussing with senior engineers and develop a good understanding of what components of TB is required to be built.
2) Build testbench components in UVM, add them to existing TB, Simulate Functionality of TB components, Enabled multiple plusargs through commandlines, regress with provided RTL wrapper and make sure the testbench is sanitized and clean.
3) Review Code and waveforms with senior members as necessary.
Job Requirements :-
1) We are looking for freshers or junior engineers who can code RTL and sub-unit Testbench from scratch with engineering supervision and broad level Microachitecture and Architecture Specs.
2) The person needs to have an excellent/good Verilog/SystemVerilog/Perl Skillset.The coding will be Perl mixed Verilog/SV.
3) Knowledge of Make, Python, Bash is an advantage, but not mandatory.
4) The person needs to have a good understanding of the basic building blocks of an ASIC/FPGA design. Understanding of advanced concepts (as coherency) is an advantage, but not mandatory.
5) The person should have good energy to finish work in a timely manner, passion for RTL/TB coding, attention to details and humility to learn from right feedback.
Who can Apply :-
1) Fresher/junior engineers looking for an opportunity.
2) People looking for training/upscaling in the domain can apply.
3) People looking to explore in-depth from scratch ASIC design can also apply.
Benefits :-
1) Opportunity to work in complex ASIC product design from scratch.
2) Opportunity to learn alongside experienced and passionate engineers.
3) Monthly Stipend/Remuneration.
4) Facility to work remotely.
How To Apply :-
Please apply answering below points -
1) Your expertise level in Perl, Verilog, System Verilog - Beginner/Intermediate/Expert.
2) Which area between design/verification you are more interested in.
Placeholder budget/timeline. Details to be discussed.
If you are sending a proposal, please be available in chat so that details can be discussed.
Development of PCIe Logical Physical Layer Testbench Components :-
1) Go through PCIE gen 5 spec, existing TB Architecture by both reading and discussing with senior engineers and develop a good understanding of what components of TB is required to be built.
2) Build testbench components in UVM, add them to existing TB, Simulate Functionality of TB components, Enabled multiple plusargs through commandlines, regress with provided RTL wrapper and make sure the testbench is sanitized and clean.
3) Review Code and waveforms with senior members as necessary.
Job Requirements :-
1) We are looking for freshers or junior engineers who can code RTL and sub-unit Testbench from scratch with engineering supervision and broad level Microachitecture and Architecture Specs.
2) The person needs to have an excellent/good Verilog/SystemVerilog/Perl Skillset.The coding will be Perl mixed Verilog/SV.
3) Knowledge of Make, Python, Bash is an advantage, but not mandatory.
4) The person needs to have a good understanding of the basic building blocks of an ASIC/FPGA design. Understanding of advanced concepts (as coherency) is an advantage, but not mandatory.
5) The person should have good energy to finish work in a timely manner, passion for RTL/TB coding, attention to details and humility to learn from right feedback.
Who can Apply :-
1) Fresher/junior engineers looking for an opportunity.
2) People looking for training/upscaling in the domain can apply.
3) People looking to explore in-depth from scratch ASIC design can also apply.
Benefits :-
1) Opportunity to work in complex ASIC product design from scratch.
2) Opportunity to learn alongside experienced and passionate engineers.
3) Monthly Stipend/Remuneration.
4) Facility to work remotely.
How To Apply :-
Please apply answering below points -
1) Your expertise level in Perl, Verilog, System Verilog - Beginner/Intermediate/Expert.
2) Which area between design/verification you are more interested in.
Placeholder budget/timeline. Details to be discussed.
If you are sending a proposal, please be available in chat so that details can be discussed.
Related categories:
Perl
Verilog / VHDL
Very-large-scale integration (VLSI)
FPGA Coding
Digital ASIC Coding