ExaNIC HFT Latency Optimization

I run a high-frequency trading stack built around Exablaze ExaNIC adapters and I need an expert who can squeeze every last micro- and preferably nanosecond out of the network path. The application is an HPC-grade trading engine, already functional, but I’m looking for deep system-level optimisation rather than new feature work.

The immediate goal is to analyse the current kernel-bypass pipeline, tune firmware and driver settings, and refine the userspace networking code so packet transit from wire to strategy logic is as close to zero-copy and zero-latency as the hardware allows. You should be comfortable working in C/C++ under low-latency Linux kernels, familiar with libexanic.
Deliverables
Code to preload the orders on exanic
Acceptance criteria: measurable reduction in average and tail latency under synthetic traffic loads, demonstrated with the test harness on identical hardware to the baseline run.

I can provide remote access to a dedicated test server equipped with two ExaNIC X10 & X25 cards, sub-us time source and traffic generators. I’m ready to start as soon as we agree on milestones and a realistic timeframe for initial results.

You will need to complete the preload part of the attached code.