Industrial Multilayer PCB: MCU & FPGA
Budget: ₹12,500 – ₹37,500 INR
I’m building an industrial control system that brings an ARM Cortex-M microcontroller together with a Xilinx FPGA and a companion DSP on a compact, high-reliability multilayer board. The design calls for careful layer stack-up, controlled-impedance routing for high-speed buses between the MCU, FPGA and memory, as well as robust isolation and filtering for noisy factory environments.
I already have a block diagram and rough pin assignments; what I need now is a complete hardware package that takes the concept all the way to production-ready files.
— 6- to 10-layer schematic and PCB layout, including power architecture, differential pairs and test-point strategy
— Verified design rules for 4 mil traces / 8 mil vias (or tighter if you can justify it)
— Fabrication outputs: Gerbers, ODB++, drill files, IPC-356 netlist, layer stack table
— Assembly outputs: Pick-and-place, centroid, BOM with manufacturer part numbers and alternates
— Source files in Altium Designer (or KiCad if you prefer, as long as the above exports are provided)
— A brief design report summarising signal-integrity considerations, decoupling calculations and any simulations you run
I’ll review schematics first, then green-light the PCB layout; final acceptance happens once the board passes ERC/DRC with no violations and the fab house confirms the stack-up.
If you have prior experience mixing ARM Cortex-M devices with Xilinx parts on dense boards, I’m ready to share the existing documentation so you can get started right away.
I already have a block diagram and rough pin assignments; what I need now is a complete hardware package that takes the concept all the way to production-ready files.
— 6- to 10-layer schematic and PCB layout, including power architecture, differential pairs and test-point strategy
— Verified design rules for 4 mil traces / 8 mil vias (or tighter if you can justify it)
— Fabrication outputs: Gerbers, ODB++, drill files, IPC-356 netlist, layer stack table
— Assembly outputs: Pick-and-place, centroid, BOM with manufacturer part numbers and alternates
— Source files in Altium Designer (or KiCad if you prefer, as long as the above exports are provided)
— A brief design report summarising signal-integrity considerations, decoupling calculations and any simulations you run
I’ll review schematics first, then green-light the PCB layout; final acceptance happens once the board passes ERC/DRC with no violations and the fab house confirms the stack-up.
If you have prior experience mixing ARM Cortex-M devices with Xilinx parts on dense boards, I’m ready to share the existing documentation so you can get started right away.