Simulink-FPGA HIL Guidance System

I’m starting my final-year project by taking the MathWorks example “Designing a Guidance System in MATLAB and Simulink” and turning it into a hardware-in-the-loop demonstration that off-loads the control algorithms onto an FPGA—ideally the Altera DE2-115 I already have on my desk. Right now I’m at the initial setup stage, so everything is still in pure Simulink.

Your role is to guide me through the FPGA-in-the-Loop (FIL) workflow, get the controller blocks synthesised, and prove they behave identically once they’re running on silicon. Sensor integration and data logging can wait; the immediate focus is control-algorithm work and, in particular, thorough algorithm testing after it lands on the chip.

Deliverables
• Partitioned Simulink model with the guidance/control section prepared for HDL Coder
• Synthesizable VHDL/Verilog project targeted to the DE2-115 and built in Quartus
• Configured Simulink FIL interface (JTAG link, board files, timing setup)
• Automated test bench in Simulink that compares host versus FPGA outputs and confirms fixed-point accuracy
• Short, clear setup guide so I can reproduce every step on my own machine

Acceptance criteria
The closed-loop simulation must run in real time with the FPGA in the loop, and host-vs-FPGA numerical differences must stay within ±1 LSB for the supplied test vectors.

If you’re comfortable with Simulink, HDL Coder, Quartus, and real-time verification on the DE2-115, let’s discuss how we can move forward.