MESI protocol mini project

Using MESI protocol, write the state transition between the three processors (P0, P1 and P2).
In the attach picture, we can see list of the instruction that we need to follow. Instructions that are used:
LD - load, ADD, SUB - subtraction, ST - store.
The most important part is to describe for each transition, what is the current state of the registers in cache.
What are the changes during every transition? So, basically the changes of the registers.
For example, first transition is Exclusive state for P0. Comment for that transition: Value from memory location 3 will be placed in R1 register (R1=0x33). This is the read miss, because cache was initially empty and we need to fetch block from main memory and put it in the cache. Follow this form of the comment for each transition. Assume that all caches are initially empty. All initial register values are 0.
This are the values of the memory from location 0 to location 4:
0 - 0x00
1 - 0x11
2 - 0x22
3 - 0x33
4 - 0x44