KiCad ESP32 Two-Layer PCB Gerbers

I already have a complete circuit schematic for an ESP32-based board and now need it translated into production-ready, two-layer Gerber files. Please work exclusively in KiCad so that I can review and maintain the project later.

Follow standard IPC design rules throughout: clearances, trace widths, copper pours, silkscreen legibility, and all the usual checks that guarantee a smooth hand-off to any mainstream fab house. The board carries an ESP32 module, its accompanying power-management stage (regulators, protection, filtering), plus several sensors and small actuators. Placement should reflect good RF practice around the ESP32 antenna while keeping analog and noisy digital sections apart.

I will supply:
• the schematic (KiCad or PDF)
• component datasheets and footprints when they are not in the KiCad default libraries

You will return:
• the complete KiCad project folder
• Gerber, drill, and pick-and-place files ready for upload to JLCPCB or similar
• a concise BOM and rendering so I can double-check part orientation

The board must pass KiCad DRC with no errors or warnings and respect 2-layer manufacturability. If small schematic tweaks are essential for routing, flag them first. Looking forward to a clean, compact layout I can send straight to the fab.
Crucial: The board controls a 12V/5A Peltier load. Power traces must be calculated for 5A current capacity (minimum 80-100 mil width or equivalent copper pour) to ensure thermal safety.