Design Valve Controller PCB
Budget: ₹1,500 – ₹12,500 INR
Valve Controller PCB Requirements v2.0 – Agriscience Aligned
Project: Agriscience IoT – Smart Valve Controller Node
Goal: Design a solar-powered, low-power, LoRa-enabled latching valve controller compatible with Agriscience’s ecosystem of soil and weather telemetry nodes. The controller must integrate robust protections, allow manual operation, and support OTA-safe firmware behavior.
1) Scope & Deliverables
Deliver a complete KiCad 8 design pack optimized for JLCPCB/PCBWay fabrication: • Manufacturing: Gerbers, drill files, IPC netlist, BOM (LCSC MPNs), and pick-place files. • Assembly: Drawings, reference photos, test points, and polarity maps. • Firmware bring-up: Demonstrate Boost_EN, valve actuation, gated LoRa, ADC read, and V_SENSE control. • Sleep-current and valve tests must be validated with acceptance report.
2) System Architecture & Core Components
MCU: ESP32-WROOM-32D LoRa: EBYTE E32-900T20D (868 MHz UART) Valve Driver: DRV8833 (latching 9 V) Boost Converter: XL6009 (9 V @ ≥1 A pulse) Battery Management: CN3065 Solar Li-ion charger 3.3 V Regulator: Low-Iq buck (≤10 µA Iq) External Watchdog: TPS3435 (window type) Voltage Supervisor: TPS3890 (3.05–3.1 V) Load Switches: TPS22910A (LoRa + sensor rails) Protections: TVS (Solar ≥SMBJ24A, Valve SMAJ12A), reverse-PMOS ideal diode at battery
3) Power Management & Low Power Targets
Mandatory total sleep current: ≤150 µA. • ESP32 deep sleep ≤10 µA • Regulator Iq ≤10 µA • LoRa load switch OFF ≤1 µA • WDT + Supervisor ≤5 µA total • ADC divider gated (0 µA when OFF) Boost_EN must be LOW in sleep (pulldown resistor mandatory). Bulk capacitance: ≥1000 µF on +9V_VALVE. Reverse polarity via PMOS ideal diode on battery input; Schottky (SS34) only on solar input.
4) Reliability, Watchdog & Supervisor
TPS3435 watchdog must reset ESP32 EN when WDI stops toggling. TPS3890 supervisor monitors 3V3; asserts EN low below ~3.05 V. Both devices must have DNP option footprints. Firmware must periodically kick WDI (GPIO32 preferred). Board must recover automatically after brownout or hang conditions.
5) Connectors & I/O
• BAT IN: JST-VH 2-pin (VBAT, GND) • SOLAR IN: JST-VH 2-pin (SOL+, GND) • VALVE OUT: 2-pin 5.08 mm terminal (Valve_A, Valve_B) • UART Header: 6-pin (3V3, GND, TX0, RX0, EN, IO0) • Sensor Header: 6-pin (V_SENSE 3V3 gated, GND, ADC1, SDA, SCL, GPIO_spare) • LoRa Antenna: U.FL connector with 50 Ω trace & RF keep-out • Manual Switch: 3-pin header for ON/OFF/Auto modes
6) ESP32 Pin Map
• GPIO26 → Valve_A (DRV8833 IN_A) • GPIO27 → Valve_B (DRV8833 IN_B) • GPIO14 → Boost_EN • GPIO25 → LoRa_SW (TPS22910A) • GPIO15 → V_SENSE gate • GPIO32 → Watchdog WDI • GPIO35 → ADC_BAT (via gated divider) • GPIO16/17 → LoRa RX/TX (UART2) • GPIO4 → LoRa AUX (ready) • GPIO21/22 → I²C (SDA/SCL) • EN pin tied to TPS3890 + WDT reset outputs
7) Software & Telemetry Alignment
The firmware must publish unified telemetry JSON with these keys: { "vbat": float(VBAT), "boost_en": 0|1, "valve_status": "OPEN/CLOSE", "valve_age_ms": uptime, "rssi": LoRaRSSI } Manual override switch state must be logged with timestamp. OTA updates must be refused when VBAT < 3.6 V. Valve pulses must not induce ESP brownouts at VBAT ≥3.5 V.
8) Acceptance Criteria
• Sleep current ≤150 µA @ 25°C • Valve actuation without brownout ≥3.5 V • LoRa ping successful within 5 s of wake • WDT-induced reset verified • OTA blocked below 3.6 V • V_SENSE toggles cleanly with GPIO15 • Manual switch logs OPEN/CLOSE with timestamp
9) Environmental & Mechanical
Copper weight: 1 oz both layers, 6/6 mil min rules. Star grounding between high-current and MCU planes. Conformal coating or IP65 enclosure required. Board size target ≤60×80 mm, 3.2 mm mount holes. DFM: All external connectors polarized and silkscreen-labeled clearly.
Project: Agriscience IoT – Smart Valve Controller Node
Goal: Design a solar-powered, low-power, LoRa-enabled latching valve controller compatible with Agriscience’s ecosystem of soil and weather telemetry nodes. The controller must integrate robust protections, allow manual operation, and support OTA-safe firmware behavior.
1) Scope & Deliverables
Deliver a complete KiCad 8 design pack optimized for JLCPCB/PCBWay fabrication: • Manufacturing: Gerbers, drill files, IPC netlist, BOM (LCSC MPNs), and pick-place files. • Assembly: Drawings, reference photos, test points, and polarity maps. • Firmware bring-up: Demonstrate Boost_EN, valve actuation, gated LoRa, ADC read, and V_SENSE control. • Sleep-current and valve tests must be validated with acceptance report.
2) System Architecture & Core Components
MCU: ESP32-WROOM-32D LoRa: EBYTE E32-900T20D (868 MHz UART) Valve Driver: DRV8833 (latching 9 V) Boost Converter: XL6009 (9 V @ ≥1 A pulse) Battery Management: CN3065 Solar Li-ion charger 3.3 V Regulator: Low-Iq buck (≤10 µA Iq) External Watchdog: TPS3435 (window type) Voltage Supervisor: TPS3890 (3.05–3.1 V) Load Switches: TPS22910A (LoRa + sensor rails) Protections: TVS (Solar ≥SMBJ24A, Valve SMAJ12A), reverse-PMOS ideal diode at battery
3) Power Management & Low Power Targets
Mandatory total sleep current: ≤150 µA. • ESP32 deep sleep ≤10 µA • Regulator Iq ≤10 µA • LoRa load switch OFF ≤1 µA • WDT + Supervisor ≤5 µA total • ADC divider gated (0 µA when OFF) Boost_EN must be LOW in sleep (pulldown resistor mandatory). Bulk capacitance: ≥1000 µF on +9V_VALVE. Reverse polarity via PMOS ideal diode on battery input; Schottky (SS34) only on solar input.
4) Reliability, Watchdog & Supervisor
TPS3435 watchdog must reset ESP32 EN when WDI stops toggling. TPS3890 supervisor monitors 3V3; asserts EN low below ~3.05 V. Both devices must have DNP option footprints. Firmware must periodically kick WDI (GPIO32 preferred). Board must recover automatically after brownout or hang conditions.
5) Connectors & I/O
• BAT IN: JST-VH 2-pin (VBAT, GND) • SOLAR IN: JST-VH 2-pin (SOL+, GND) • VALVE OUT: 2-pin 5.08 mm terminal (Valve_A, Valve_B) • UART Header: 6-pin (3V3, GND, TX0, RX0, EN, IO0) • Sensor Header: 6-pin (V_SENSE 3V3 gated, GND, ADC1, SDA, SCL, GPIO_spare) • LoRa Antenna: U.FL connector with 50 Ω trace & RF keep-out • Manual Switch: 3-pin header for ON/OFF/Auto modes
6) ESP32 Pin Map
• GPIO26 → Valve_A (DRV8833 IN_A) • GPIO27 → Valve_B (DRV8833 IN_B) • GPIO14 → Boost_EN • GPIO25 → LoRa_SW (TPS22910A) • GPIO15 → V_SENSE gate • GPIO32 → Watchdog WDI • GPIO35 → ADC_BAT (via gated divider) • GPIO16/17 → LoRa RX/TX (UART2) • GPIO4 → LoRa AUX (ready) • GPIO21/22 → I²C (SDA/SCL) • EN pin tied to TPS3890 + WDT reset outputs
7) Software & Telemetry Alignment
The firmware must publish unified telemetry JSON with these keys: { "vbat": float(VBAT), "boost_en": 0|1, "valve_status": "OPEN/CLOSE", "valve_age_ms": uptime, "rssi": LoRaRSSI } Manual override switch state must be logged with timestamp. OTA updates must be refused when VBAT < 3.6 V. Valve pulses must not induce ESP brownouts at VBAT ≥3.5 V.
8) Acceptance Criteria
• Sleep current ≤150 µA @ 25°C • Valve actuation without brownout ≥3.5 V • LoRa ping successful within 5 s of wake • WDT-induced reset verified • OTA blocked below 3.6 V • V_SENSE toggles cleanly with GPIO15 • Manual switch logs OPEN/CLOSE with timestamp
9) Environmental & Mechanical
Copper weight: 1 oz both layers, 6/6 mil min rules. Star grounding between high-current and MCU planes. Conformal coating or IP65 enclosure required. Board size target ≤60×80 mm, 3.2 mm mount holes. DFM: All external connectors polarized and silkscreen-labeled clearly.