iCE40 DVB PID Filter Module

I need a compact DVB packet processor written in Verilog that runs on a Lattice iCE40 FPGA. The sole task is packet filtering—specifically PID filtering—restricted to one selected PID at a time.

Scope
• RTL design in clean, synth-ready Verilog targeting the iCE40 HX or UP family
• Functional testbench that feeds 188-byte TS packets, demonstrates correct acceptance of the chosen PID, and drops everything else.
• Synthesis script (nextpnr + IceStorm or Lattice Radiant) showing timing closure at 27 MHz TS clock or better.
• Resource-usage report so I can judge fit against the device’s limited LUT/BRAM budget.
• Simple register or constant that lets me change the target PID before build time; run-time reconfiguration via a small wishbone or APB slave would be a welcome bonus but is not mandatory.
• Brief markdown document explaining module ports, clock/reset assumptions, and how to replicate your test results.

Acceptance
The design must:
1. Pass simulation with a mixed-PID transport stream (golden VCD or waveform).
2. Synthesize and place-and-route on an iCE40 8k device (or smaller) while meeting timing.
3. Output a valid bitstream along with the artifacts above.

If you have experience squeezing efficient logic into iCE40s and can hand over well-commented, lint-clean code, I’d love to work with you.