Xilinx Artix 7 FPGA Core Porting

We are seeking an experienced FPGA engineer to handle the initial phase of a multi-stage project focused on porting an open-source HDL core from Altera Cyclone III/V FPGAs to a Xilinx Artix-7 device. This phase will target the Digilent Arty A7-100T development board (XC7A100T FPGA with 256MB DDR3) as a proof-of-concept prototype. The core, which requires approximately 25,000 logic elements, emulates a classic computing chipset and includes features like VGA output, PS/2 input, SD card support for disk emulation, and 16-bit memory integration. The goal is to achieve a stable, functional implementation using Xilinx Vivado tools, with adaptations for vendor-specific primitives, memory interfacing, and basic peripherals.
This is a remote freelance opportunity, ideal for someone with strong porting skills across FPGA vendors. The deliverable will be a working bitstream, updated source code repository, and documentation of the process. Estimated timeline: 2-4 weeks, depending on experience.

Key Responsibilities:
• Acquire and adapt open-source HDL code (primarily Verilog/VHDL) from repositories like MiSTer-devel or similar community projects, converting Altera-specific elements (e.g., PLLs, Block RAM) to Xilinx equivalents (e.g., MMCMs).
• Integrate DDR3 memory using Xilinx MIG IP for various RAM mappings (e.g., up to 128MB configurations).
• Update constraint files (XDC) for the Arty A7-100T pinout, including 100MHz clock, USB UART, and Pmod connectors for initial I/O testing (e.g., VGA, keyboard/mouse).
• Synthesize and build the bitstream in Vivado (WebPACK edition), aiming for 70-80% resource utilization.
• Test core functionality, including CPU emulation (68000), graphics output, and SD card-based storage emulation.
• Debug timing issues, resource constraints, and signal integrity using tools like Vivado Logic Analyzer.
• Document the porting steps, adaptations, and testing results for future phases.

Requirements:
• At least 3 years of hands-on FPGA development experience, with expertise in Xilinx Artix-7 or similar families using Vivado.
• Proficiency in VHDL and Verilog for core adaptation and optimization.
• Experience porting FPGA cores between vendors (e.g., Altera to Xilinx), including handling I/O configurations, clocking differences, and size constraints.
• Familiarity with embedded systems integration, including custom peripherals and memory controllers.
• Strong debugging skills with tools like ChipScope or Vivado analyzers for troubleshooting performance and efficiency.
• Access to a Digilent Arty A7-100T board for development and testing (required; we will not provide hardware for this phase).
• Bonus: Active in FPGA or retro computing communities (e.g., MiSTer forums or open-source repos), with knowledge of similar cores like those in ranzbak/MinimigAGA_TC64 or gyurco/Minimig-AGA.

Preferred Skills:
• Experience with DDR3 interfacing via MIG IP.
• Knowledge of open-source FPGA emulation projects and community-driven ports.
• Ability to optimize for timing closure and resource efficiency on 28nm architectures.
If you have the expertise and hardware access, please apply with your relevant portfolio, examples of past porting projects, and an estimated quote/timeline. We value clear communication and milestone-based progress updates.