VHDL FPGA & Python Automation
Budget: €300 – €350 EUR
I’m expanding an FPGA project and need someone who can move comfortably between VHDL development and quick-turn Python scripting. On the FPGA side, the immediate task is to write, tidy up, and document VHDL modules, then verify them in simulation and on hardware. Alongside that, I’d like lightweight Python utilities to automate synthesis runs, manage bitstream builds, and trigger scripted tests so I can iterate without manual intervention.
You’ll be handed my current repo (Vivado-based, with ModelSim testbenches) plus a short list of new features. From there I expect:
• well-structured VHDL that meets timing in a mid-range Xilinx device
• Python scripts (Python 3) that call the usual vendor CLI tools, gather logs, and flag errors automatically
• clean, commented code pushed via Git so I can review each milestone quickly
If you’ve previously tied together VHDL flows with Python (think TCL wrappers, pytest, or simple Makefile replacements), this will feel familiar. Let me know when you can start and which FPGA boards you have on hand for local testing; I’ll match mine to yours where possible.
You’ll be handed my current repo (Vivado-based, with ModelSim testbenches) plus a short list of new features. From there I expect:
• well-structured VHDL that meets timing in a mid-range Xilinx device
• Python scripts (Python 3) that call the usual vendor CLI tools, gather logs, and flag errors automatically
• clean, commented code pushed via Git so I can review each milestone quickly
If you’ve previously tied together VHDL flows with Python (think TCL wrappers, pytest, or simple Makefile replacements), this will feel familiar. Let me know when you can start and which FPGA boards you have on hand for local testing; I’ll match mine to yours where possible.