SystemVerilog Capacitive Sensor Module
Budget: $30 – $250 USD
I’m building a small proof-of-concept that turns the raw analog voltage from a capacitive proximity sensor into a clean Near/Far decision with hysteresis and streams that result over a UART link to my computer. The entire design must be written in synthesizable SystemVerilog and kept intentionally simple so it compiles easily in a standard FPGA flow (ModelSim/Vivado/Quartus—your choice).
Key points you’ll handle
• Sample an external ADC value that represents sensor capacitance.
• Convert that value to a Near or Far state using sensible default thresholds and add hysteresis so the output doesn’t chatter.
• Transmit “NEAR\r\n” or “FAR\r\n” (or similarly short strings) via a 1-stop-bit, 8-N-1 UART.
• Make thresholds easy to tweak in a single parameter declaration.
Please include a concise design report (2–4 pages) outlining the algorithm, threshold rationale, UART settings, RTL hierarchy, and simulation results.
Deliverables
1. Clean, synthesizable SystemVerilog source and a simple top-level wrapper.
2. Self-checking testbench that toggles the input voltage around the thresholds to demonstrate hysteresis and shows the corresponding UART output.
3. The PDF report described above.
Acceptance criteria: all files compile with no errors or timing violations in the chosen toolchain, the testbench waveform/console clearly shows correct Near/Far behaviour with hysteresis, and the UART frames match the expected strings.
Key points you’ll handle
• Sample an external ADC value that represents sensor capacitance.
• Convert that value to a Near or Far state using sensible default thresholds and add hysteresis so the output doesn’t chatter.
• Transmit “NEAR\r\n” or “FAR\r\n” (or similarly short strings) via a 1-stop-bit, 8-N-1 UART.
• Make thresholds easy to tweak in a single parameter declaration.
Please include a concise design report (2–4 pages) outlining the algorithm, threshold rationale, UART settings, RTL hierarchy, and simulation results.
Deliverables
1. Clean, synthesizable SystemVerilog source and a simple top-level wrapper.
2. Self-checking testbench that toggles the input voltage around the thresholds to demonstrate hysteresis and shows the corresponding UART output.
3. The PDF report described above.
Acceptance criteria: all files compile with no errors or timing violations in the chosen toolchain, the testbench waveform/console clearly shows correct Near/Far behaviour with hysteresis, and the UART frames match the expected strings.