Streamline PolarFire Dual-Camera FPGA
Budget: $30 – $250 USD
I have Microchip’s PolarFire reference project running two cameras, and the current data-processing stage is far heavier than I need. Your task is to open up the Verilog / VHDL sources, strip away most of the image-processing features, and leave me with a lean pipeline that simply brings raw frames through with only the minimal logic required for downstream use. Camera interfaces and communication links are already stable, so nothing there should change.
You’ll be editing the existing HDL, rebuilding the project in Libero, and handing back a clean compile plus a short simulation that proves the slimmed-down design still meets timing and outputs valid video on both channels. If you can push code to a Git repo and include a short read-me explaining which modules were removed or simplified, that will be perfect.
You’ll be editing the existing HDL, rebuilding the project in Libero, and handing back a clean compile plus a short simulation that proves the slimmed-down design still meets timing and outputs valid video on both channels. If you can push code to a Git repo and include a short read-me explaining which modules were removed or simplified, that will be perfect.