Simple Verilog to VHDL Conversion for FPGA

I need someone to convert a simple Verilog code into VHDL for FPGA implementation. The design is straightforward, so it doesn't involve intricate logic or multiple modules.

Ideal skills and experience include:
- Proficiency in Verilog and VHDL
- Experience with FPGA design
- Ability to understand and convert basic code

Please note, this is a simple task and does not require dealing with complex designs or systems.