Pcileech FPGA PCIe/USB Customization and Verification

Use the PCILeech-FPGA project as a base to implement a PCIe device that supports both PCILeech DMA and functions as an xHCI host controller following the Intel xHCI specification. The device must expose valid xHCI capability, operational, and runtime registers, implement command/event/transfer ring logic, and present a virtual root hub with one USB HID device. The HID device must be changeable at runtime and support standard USB enumeration and interrupt-based report transfers. The FPGA must also fully support PCILeech DMA memory read/write operations as expected by existing PCILeech tooling.

Deliverables include the FPGA HDL source, bitstream, and supporting firmware. A host-side tool must be provided to switch the active HID device type and feed report data. The deliverables must also include a method to dump USB HID devices from a real system (e.g. using USBPcap or similar tools), convert the captured descriptors and behaviors into a usable format, and load them into the emulated HID slot dynamically. Test cases must demonstrate enumeration under Windows and Linux, successful PCILeech DMA access, HID device switching, and injecting real HID data from dumped profiles.